1 industrial temperature range idt5v2310 2.5v to 3.3v high performance clock buffer may 2010 2004 integrated device technology, inc. dsc 6173/25 c industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. features: ? high performance 1:10 clock driver for general purpose applications ? operates up to 200mhz at v dd = 3.3v ? pin-to-pin skew < 100ps ?v dd range: 2.3v to 3.6v ? output enable glitch suppression ? distributes one clock input to two banks of five outputs ?25 ? ? ? ? ? on-chip series dampening resistors ? available in tssop and vfqfpn packages functional block diagram idt5v2310 2.5v to 3.3v high performance clock buffer description: the idt5v2310 is a high performance, low skew clock buffer that operates up to 200mhz. two banks of five outputs each provide low skew copies of clk. through the use of control pins 1g and 2g, the outputs of banks 1y(0:4) and 2y(0:4) can be placed in a low state regardless of clk input. the device operates in 2.5v and 3.3v environments. the built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals. the idt5v2310 is characterized for operation from -40c to +85c. 25 3 1 y 0 25 4 1 y 1 25 5 1 y 2 25 8 1 y 3 25 9 1 y 4 logic control 1g 11 25 12 2 y 4 25 16 2 y 3 25 17 2 y 2 25 20 2 y 1 25 21 2 y 0 logic control 2g 13 clk 24
2 industrial temperature range idt5v2310 2.5v to 3.3v high performance clock buffer pin configuration tssop top view function table (1) note: 1. h = high voltage level l = low voltage level x = don?t care inputs outputs 1g 2g clk 1 y (0:4) 2 y (0:4) llx l l hlh h l lhh l h hhh h h capacitance (t a = +25c, f = 1mhz, v in = 0v) parameter description min. typ. max. unit c in input capacitance ? 2.5 ? pf v i = 0v or v dd symbol description max unit v dd power supply voltage ?0.5 to +4.6 v v i input voltage (2) ?0.5 to v dd +0.5 v v o output voltage (2) ?0.5 to v dd +0.5 v i ik input clamp current 50 ma v i < 0 or v i > v dd i ok output clamp current 50 ma v o < 0 or v o > v dd i o continuous total output current 50 ma v o < 0 to v dd t stg storage temperature ?65 to +150 c absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. not to exceed 4.6v. vfqfpn top view c l k v d d 2 y 4 2 g v dd 1 y 1 1 y 0 1 y 2 1 y 4 v dd 1 g v dd v dd 2 y 1 2 y 0 2 y 2 2 y 3 v dd v dd 2 3 4 5 6 7 8 11 10 9 19 18 17 16 15 14 13 12 120 1 y 3 gnd gnd v dd 1 y 1 1 y 0 1 y 2 gnd gnd 1 y 3 1 y 4 v dd 1g 2 y 4 clk v dd 2 y 0 v dd 2 y 1 gnd gnd 2 y 2 2 y 3 v dd v dd 2g 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
3 industrial temperature range idt5v2310 2.5v to 3.3v high performance clock buffer symbol description min. typ. max. unit v dd internal power supply voltage 2.3 2.5 v 3.3 3.6 v il input voltage low v dd = 3v to 3.6v 0.8 v v dd = 2.3v to 2.7v 0.7 v ih input voltage high v dd = 3v to 3.6v 2 v v dd = 2.3v to 2.7v 1.7 v i input voltage 0 v dd v i oh output current high v dd = 3v to 3.6v -12 ma v dd = 2.3v to 2.7v -6 i ol output current low v dd = 3v to 3.6v 12 ma v dd = 2.3v to 2.7v 6 t a ambient operating temperature -40 +85 c recommended operating range note: 1. all typical values are at respective nominal v dd . dc electrical characteristics - v dd = 3.3v 0.3v symbol parameter test conditions min. typ. (1) max unit v dd = min. to max. i oh = -100 av dd - 0.2 v oh high level output voltage v dd = 3v i oh = -12ma 2.1 v i oh = -6ma 2.4 v dd = min. to max. i ol = 100 a 0.2 v ol low level output voltage v dd = 3v i ol = 12ma 0.8 v i ol = 6ma 0.55 v dd = 3v v o = 1v -28 i oh high level output current v dd = 3.3v v o = 1.65v -36 ma v dd = 3.6v v o = 3.135v -14 v dd = 3v v o = 1.95v 28 i ol low level output current v dd = 3.3v v o = 1.65v 36 ma v dd = 3.6v v o = 0.4v 14 note: 1. for i dd over frequency, see test circuit and waveforms. dc electrical characteristics over operating range symbol parameter test conditions min. typ. max unit v ik input voltage v dd = 3v, i in = -18ma - 1.2 v i in input current v i = 0v or v dd 5 a i dd static device current (1) clk = 0v or v dd , i o = 0ma, v dd = 3.3v 25 a pin description terminal symbol i/o description 1g i output enable control for 1 y (0:4) outputs. this output enable is active high. if this pin is logic high, the 1 y (0:4) clock outputs will follow the input clock (clk). if this pin is logic low, the 1 y (0:4) outputs will drive low independent of the state of clk. 2g i output enable control for 2 y (0:4) outputs. this output enable is active high. if this pin is logic high, the 2 y (0:4) clock outputs will follow the input clock (clk). if this pin is logic low, the 2 y (0:4) outputs will drive low independent of the state of clk. 1 y (0:4) o buffered output clocks 2 y (0:4) o buffered output clocks clk i input reference frequency gnd ground v dd pwr dc power supply, 2.3v to 3.6v
4 industrial temperature range idt5v2310 2.5v to 3.3v high performance clock buffer note: 1. all typical values are at respective nominal v dd . dc electrical characteristics - v dd = 2.5v 0.2v symbol parameter test conditions min. typ. (1) max unit v oh high level output voltage v dd = min. to max. i oh = -100 av dd - 0.2 v v dd = 2.3v i oh = -6ma 1.8 v ol low level output voltage v dd = min. to max. i ol = 100 a 0.2 v v dd = 2.3v i ol = 6ma 0.55 v dd = 2.3v v o = 1v -17 i oh high level output current v dd = 2.5v v o = 1.25v -25 ma v dd = 2.7v v o = 2.375v -10 v dd = 2.3v v o = 1.2v 17 i ol low level output current v dd = 2.5v v o = 1.25v 25 ma v dd = 2.7v v o = 0.3v 10 timing requirements over recommended range symbol parameter test conditions min. typ. max unit f clk clock frequency v dd = 3v to 3.6v 0 200 mhz v dd = 2.3v to 2.7v 0 170
5 industrial temperature range idt5v2310 2.5v to 3.3v high performance clock buffer switching characteristics over operating range - v dd = 2.5v 0.2v (1) symbol parameter test conditions min. typ. (1) max unit t plh clk to yx f = 0mhz to 170mhz 1.5 3.5 ns t phl t sk ( o ) (2) output skew, yx to yx 100 ps t sk ( p ) pulse skew 400 ps t sk ( pp ) part-to-part skew 600 ps t r rise time v o = 0.4v to 1.7v (3) 0.5 1.4 v/ns t f fall time v o = 1.7v to 0.4v (3) 0.5 1.4 v/ns t su g before clk v( threshold ) = v dd /2 0.1 ns t h g after clk 0.4 notes: 1. all typical values are at respective nominal v dd . 2. this specification is only valid for equal loading of all outputs. 3. measured at 100mhz. switching characteristics over operating range - v dd = 3.3v 0.3v (1) symbol parameter test conditions min. typ. (1) max unit t plh clk to yx f = 0mhz to 200mhz 1.3 2.8 ns t phl t sk ( o ) (2) output skew, yx to yx 100 ps t sk ( p ) pulse skew 250 ps t sk ( pp ) part-to-part skew 500 ps t r rise time v o = 0.4v to 2v (3) 0.7 2 v/ns t f fall time v o = 2v to 0.4v (3) 0.7 2 v/ns t su g before clk v( threshold ) = v dd /2 0.1 ns t h g after clk 0.4 notes: 1. all typical values are at respective nominal v dd . 2. this specification is only valid for equal loading of all outputs. 3. measured at 100mhz.
6 industrial temperature range idt5v2310 2.5v to 3.3v high performance clock buffer output enable glitch suppression circuit the purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the clock input su ch that the output buffer will be enabled on the next full period of the input clock (negative edge triggered by the input clock). the g input must be stable on e t en - time prior to the falling edge of the clk for predictable operation. g (t en , t dis ) relative to clk clk t en t dis gx yx
7 industrial temperature range idt5v2310 2.5v to 3.3v high performance clock buffer test load circuit output skew test circuits and waveforms voltage waveforms propagation delay times pulse skew notes: 1. c l includes probe and jig capacitance. 2. all input pulses are supplied by generators having the following characteristics: prr 200mhz; z o = 50 ? ; t r < 1.2ns; t f < 1.2ns. clk v dd 50% v dd 0v t plh t phl 1.7v or 2v 0.4v 0.4v t r t f v oh 50% v dd v ol yx clk v dd 0v v oh v oh v ol v ol 50% v dd 50% v dd t sk(o) t sk(o) any y any y v dd v oh 0v v ol 50% v dd 50% v dd t plh t phl clk yx t sk(p) =t plh t phl from output under test c l 500
8 industrial temperature range idt5v2310 2.5v to 3.3v high performance clock buffer recommended landing pattern nr 20 pin note: all dimensions are in millimeters.
9 industrial temperature range idt5v2310 2.5v to 3.3v high performance clock buffer ordering information corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 clockhelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com 5v2310pggi tubes 24-pin tssop -40 to +85c 5v2310pggi8 tape & reel 24-pin tssop -40 to +85c 5v2310nrgi tubes 20-pin vfqfpn -40 to +85c 5V2310NRGI8 tape & reel 20-pin vfqfpn -40 to +85c
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